"For the design of COMS gate, please refer to 74hc series. During the design, the leakage current of the pipe can not be ignored, and the actual current of IO port is also different at different levels. The above is only the principle. In a word, it can be summarized as:" when the output is high, feed the rear input port, and when the output is low, do not feed the output port ", otherwise the excess current is fed to the cascade input port, If it is higher than the low level door limit, it is unreliable.

1. It should be large enough to save power consumption and the current filling capacity of the chip; High resistance and low current.

2. It should be small enough to ensure sufficient driving current; Low resistance and high current.

3. For high-speed circuits, excessive pull-up resistance may flatten the edge.

Considering the above three points, it is usually selected between 1K and 10K. The same is true for pull-down resistors.

The selection of pull-up resistance and pull-down resistance shall be set in combination with the characteristics of switch tube and the input characteristics of lower circuit, mainly considering the following factors:

1. Balance between driving capability and power consumption. Taking the above pull-up resistance as an example, generally speaking, the smaller the pull-up resistance, the stronger the driving ability, but the greater the power consumption. Attention should be paid to the balance between the two in design.

2. Driving requirements of lower level circuits. Similarly, taking the above pull-up resistance as an example, when the output is high, the switch is disconnected, and the pull-up resistance should be properly selected to provide sufficient current to the lower circuit.

3. High and low level setting. The threshold levels of high and low levels of different circuits will be different, and the resistance should be set appropriately to ensure that the correct level can be output. Taking the above pull-up resistance as an example, when the output is low, the switch is on, and the partial voltage of the pull-up resistance and the switch on resistance shall be below the zero level threshold.

4. Frequency characteristics. Taking the pull-up resistor as an example, the capacitance between the pull-up resistor and the drain source of the switch and the input capacitance between the lower circuit will form an "RC delay". The greater the resistance, the greater the delay. The setting of pull-up resistance shall consider the requirements of the circuit in this regard.

The setting principle of pull-down resistance is the same as that of pull-up resistance.

The output high level of OC gate is a high resistance state, and its pull-up current shall be provided by the pull-up resistance. It is set that each port of the input terminal is not greater than 100ua, the output port driving current is about 500uA, the standard working voltage is 5V, and the high-low level threshold of the input port is 0.8V (lower than this value is the low level) and 2V (high level gate limit).

When the pull-up resistor is selected: 500uax8 4K = 4.2V, that is, when it is greater than 8.4k, the output end can be pulled down below 0.8V, which is a very small resistance value, and it can‘t be pulled down again. If the driving current of the output port is large, the resistance can be reduced to ensure that it can be lower than 0.8V during pull-down. When the output is high, ignore the leakage current of the pipe. The two input ports need 200uA, 200uA x15k = 3V, that is, the pull-up resistance voltage drop is 3V, and the output port can reach 2V. This resistance value is a large resistance value, and no more than 2V. 10K is available (large voltage drop / large current, small voltage drop / small current).

The of COMS door can refer to 74hc series. In the design, the leakage current of the pipe can not be ignored, and the actual current of the IO port is also different at different levels. The above is only the principle. In a sentence, it is summarized as: "feed the rear input port when the output is high, and do not feed the output port when the output is low". Otherwise, the excess current is fed to the cascade input port, which is unreliable when it is higher than the limit of the low level gate.

In addition, the following points should be noted:

A. It depends on what device the output port drives. If the device needs high voltage and the output voltage of the output port is not enough, a pull resistance needs to be added.

B. If there is a pull-up resistor, its port is at the high level by default. If you want to control it, you must use the low level to control it. For example, the collector of the triode or the positive pole of the diode of the tristate gate circuit will control it to pull down the current of the pull-up resistor to become the low level.

C. Especially in the interface circuit, in order to obtain the determined level, this method is generally used to ensure the correct circuit state to avoid accidents. For example, in motor control, the upper and lower bridge arms of the inverter bridge cannot pass through. If they are driven by the same single chip microcomputer, the initial state must be set to prevent passing through.

When selecting the resistance, select one that is very close to the standard value after calculation.

P0 reasons for pulling up resistance include:

1. There is no pull-up resistance in port P0.

2. When P0 is the working state of I / O port, the upper FET is turned off, so the output pin floats. Therefore, when P0 is used for output line, it is open drain output.

3. Since there is no pull-up resistor in the chip and the upper FET is turned off, the port level cannot be pulled up when P0 outputs 1.

P0 is a two-way port, and other P1, P2 and P3 are quasi two-way ports. The reason why it is called "quasi two-way port" is that it needs to be prepared before reading external data. When the single chip microcomputer reads the port of the bidirectional port, it should first assign 1 to the port latch in order to turn off the FET and prevent the port from being clamped at the low level due to the on-chip FET conduction. 10K is generally selected for up and down.

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