Circuit reliability, that is, circuit robustness against electrical failure, has increasingly become the focus of IC designers. Many of these problems have been known for many years, and sometimes people feel that reliability risk is mainly a problem faced by the latest generation of manufacturing process. Admittedly, the smaller the device, the thinner the wire and the thinner the gate oxide layer are more susceptible to the influence of excessive electrical stress (EOS), and the new process generation is also more sensitive to the specific layout shape and pattern. However, if the designer believes that there is no circuit reliability problem on mature nodes, his future projects are likely to face some potential risks.

Why?

    Because even in the mature process, engineers will continue to extract performance, function, area and other relevant indicators from it in order to obtain higher return on investment (ROI). The older the manufacturing process, the less uncertainty may be, but each new design wave will cause new reliability problems due to different application requirements and environmental conditions. For example, the design of automotive and medical-related application chips is currently a new driving force for the adoption of mature manufacturing technology. These applications have completely different design requirements and working environments compared with common consumer applications that use cutting-edge manufacturing processes.

    No auto manufacturer will accept engine control chips that have not been verified under strict high temperature conditions, while pacemakers produced by medical manufacturers must work reliably in a long service life.

    In addition, some new circuit architectures have not yet been invented when mature nodes are first introduced. Including more analog circuits, higher voltage (such as 50V on cars) and higher frequency are only part of the ever-changing design requirements faced by circuit designers.

    In this way, new tools and methods are needed to ensure the circuit reliability of new and mature processes. For example, higher voltage on automotive equipment leads to higher EOS risk, so designers need to work harder to ensure that digital transistors with thinner gate oxide layer will not be connected to 50 V power supply. Not only that, circuits designed with high voltage also need to increase the spacing between layout patterns at specific positions.

    For the verification of such design, we only need to check some specific areas. If the whole chip is subject to large-spaced DRC inspection in accordance with high-voltage design rules, it will lead to extremely conservative design considerations, as well as excessive bare area and higher manufacturing costs.

Limited traditional methods

    Many design teams use user-generated marker layers or text points to check EOS problems, but this is an error-prone method, requiring designers to manually determine how the voltage changes between circuit nodes, and manually mark the correct areas that need to comply with high-voltage design rules. With the intensive revision and update of circuit functions, marker layers are extremely difficult to maintain.

    In today‘s increasingly complex chip design, we also face other risks: known failure mechanisms such as electrostatic discharge (ESD), latch-up, electromigration (EM) cannot be completely prevented by standard design practices.

    Among them, electromigration has been a problem for designers in many generations of ICs. However, the FinFET technology, which combines higher driving strength and uses thinner wires at 14/16 nm, has become another cause of circuit failure due to electromigration. Using traditional methods to check EM will consume huge computing resources. It is necessary to extract parasitic models, conduct current simulation and label the final results in every part of the chip. The common 16nm/14nm on-chip system will have billions of components, and it is assumed that the traditional inspection process will be very slow and unacceptable.

    In addition, because the oxide layer under the gate of the transistors currently manufactured is thinner, the related devices are more vulnerable to the impact of EOS. More difficult is that because of the design of modern power-saving chips, most of them adopt the multi-power-domain strategy, which means that a chip may have dozens of different power supplies. This greater complexity makes it extremely difficult to check out a complete potential EOS problem. In fact, the EOS check of the whole chip exceeds the ability of the standard circuit simulation and verification methods provided by various tools in the past.

    Reliability check of IC design (electronic engineering album)

Figure 1: Circuit inspection includes decoupling capacitor layout, geometric size matching and current density inspection.

New methods are needed to solve old problems

    In the past, designers relied on circuit simulation, design review, marker layers or text points for DRC of specific blocks, and of course, other "self created" methods to find possible circuit reliability problems.

    However, today, due to all the above challenges, to ensure that a design can avoid potential reliability problems, it needs an overall verification strategy. This strategy should be able to achieve the classification of circuit architecture and the search of relevant layout locations, parasitic resistance measurement of metal wires, current density calculation of metal wires, and DRC inspection of specific blocks.

    The artificial method is about to be replaced by the classification of executable circuit architecture, which can identify the relevant circuit nodes and their layout positions, and then perform corresponding static and dynamic analysis tools for various circuit types or problems.

    These tools can quickly and completely analyze the possible voltage of each device and each terminal. With this information, all possible voltages of the entire chip, each circuit node and its corresponding layout position can be calculated, and OVD inspection can be carried out very accurately and efficiently. That is to say, different minimum allowable distance design rules can be defined according to different voltage differences between two layout patterns and verified with this tool.

    These tools can also identify circuit nodes susceptible to electromigration and their corresponding layout positions, measure the parasitic resistance of metal wires between two points, and perform corresponding design rule verification to detect potential problems.

    In addition, because many of these problems occur in large chips, in addition to complete functions, efficient and concise verification tools are needed to quickly find out the cause of circuit errors. With the emergence of new tools with these functions, we have now seen several wafer foundries that have begun to provide relevant verification solutions in this field.

     However, this is only the beginning of a new field of EDA. It is expected that we will continue to use such tools to deal with the verification of the reliability problems of the circuit that were previously "undetectable" for a long time.