Modern high-performance delta sigma a/d and d/a audio conversion systems require a high-frequency system clock (master clock) for their conversion process, which usually exceeds 12 MHz The jitter on the clock is an important source of performance degradation of these systems. This is usually not a problem in products that include converters and crystal based clocks. However, this may be a particularly difficult problem to solve in the network audio system. The recording system is that the conversion node and the network operate at the same sampling rate or in the same clock domain. The most common way to recover a low jitter master clock in these systems is to use a phase locked loop (PLL). PLL circuit has many forms, each with its own advantages. However,

    Another method is to create a system architecture in which a/d and d/a conversion nodes operate in a local clock domain independent of the network or system clock domain. A system with an independent clock domain can be easily implemented using a sample rate converter (SRC), as shown in Figure 1. The architecture also allows the conversion process to run at a fixed sampling rate that is always higher than the network or interface sampling rate. The basic advantage of this method is that the conversion process is not affected by the interface clock jitter, and is controlled by a local jitter free crystal oscillator.

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